Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 221
PIC16(L)F1825/1829
24.3.7
OPERATION IN SLEEP MODE
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
24.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
24.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
CCP registers to their Reset states.
24.3.10
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
for more information.
TABLE 24-8:
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
APFCON1
—
—
SDO2SEL
(2)
SS2SEL
(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL
CCP1CON
P1M<1:0>
(1)
DC1B<1:0>
CCP1M<3:0>
CCP2CON
P2M<1:0>
(1)
DC2B<1:0>
CCP2M<3:0>
CCP3CON
—
—
DC3B<1:0>
CCP3M<3:0>
CCP4CON
—
—
DC4B<1:0>
CCP4M<3:0>
CCPTMRS
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
CCPR1L
Capture/Compare/PWM Register x Low Byte (LSB)
INLVLA
—
—
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
INLVLC
INLVLC7
(2)
INLVLC6
(2)
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
INTCON
GIE PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSFIE
C2IE
C1IE
EEIE
BCL1IE
—
—
CCP2IE
PIE3
—
—
CCP4IE
CCP3IE
TMR6IE
—
TMR4IE
—
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR2
OSFIF
C2IF
C1IF
EEIF
BCL1IF
—
—
CCP2IF
PIR3
—
—
CCP4IF
CCP3IF
TMR6IF
—
TMR4IF
—
PRx
Timer2/4/6 Period Register
T2CON
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
T4CON
—
T4OUTPS<3:0>
TMR4ON
T4CKPS<1:0>
T6CON
—
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
TMRx
Timer2/4/6 Module Register
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
TRISC
TRISC7
(2)
TRISC6
(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Legend:
— Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
* Page provides register information.
Note
Note
1:
Applies to ECCP modules only.
2:
PIC16(L)F1829 only.