Microchip Technology AC244045 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41440C-page 225

24.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/PxA pin, while the complementary PWM
output signal is output on the PxB pin (see 

).

This mode can be used for half-bridge applications, as
shown in 

, or for full-bridge applications,

where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in half-
bridge power devices. The value of the PDC<6:0> bits of
the PWMxCON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See

 for more details of the dead-band delay

operations.

Since the PxA and PxB outputs are multiplexed with the
PORT data latches, the associated TRIS bits must be
cleared to configure PxA and PxB as outputs.

Period

Pulse Width

td

td

PxA

PxB

td = Dead-Band Delay

Period

Note 1: At this time, the TMRx register is equal to the

PRx register.

2: Output signals are shown as active-high.

PxA

PxB

FET

Driver

FET

Driver

Load

+

-

+

-

FET

Driver

FET

Driver

V+

Load

FET

Driver

FET

Driver

PxA

PxB