Microchip Technology AC244045 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41440C-page 23

3.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by
setting bit 7 of the FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. 

demonstrates accessing the program memory via an
FSR.
The High directive will set bit<7> if a label points to a
location in program memory.

The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(

):

• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR) 
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See 

 for more information.

Data Memory uses a 12-bit address. The upper 7-bits
of the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.

3.2.1

CORE REGISTERS

The core registers contain the registers that directly
affect the basic operation of the PIC16(L)F1825/1829.
These registers are listed below:
• INDF0
• INDF1
• PCL
• STATUS
• FSR0  Low
• FSR0 High
• FSR1  Low
• FSR1 High
• BSR
• WREG
• PCLATH
• INTCON

constants

RETLW DATA0

;Index0 data

RETLW DATA1

;Index1 data

RETLW DATA2
RETLW DATA3

my_function

;… LOTS OF CODE…
MOVLW

LOW constants

MOVWF

FSR1L

MOVLW

HIGH constants

MOVWF

FSR1H

MOVIW

0[FSR1]

;THE PROGRAM MEMORY IS IN W

The core registers are the first 12
addresses of every data memory bank.