Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 255
PIC16(L)F1825/1829
A bus collision can occur on a Start condition if the
module samples the SDAx line low before asserting it
low. This does not conform to the I
module samples the SDAx line low before asserting it
low. This does not conform to the I
2
C Specification that
states no bus collision can occur on a Start.
25.4.6
STOP CONDITION
A Stop condition is a transition of the SDAx line from
low-to-high state while the SCLx line is high.
low-to-high state while the SCLx line is high.
25.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
shows waveforms for a
Restart condition.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed,
matching both high and low address bytes, the master
can issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear, or high
address match fails.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed,
matching both high and low address bytes, the master
can issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop
condition, a high address with R/W clear, or high
address match fails.
25.4.8
START/STOP CONDITION
INTERRUPT MASKING
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 25-12:
I
2
C START AND STOP CONDITIONS
FIGURE 25-13:
I
2
C RESTART CONDITION
Note:
At least one SCLx low time must appear
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
before a Stop is valid, therefore, if the SDAx
line goes low then high again while the SCLx
line stays high, only the Start condition is
detected.
SDAx
SCLx
P
Stop
Condition
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
Restart
Condition
Sr
Change of
Data Allowed
Change of
Data Allowed