Microchip Technology AC244045 Data Sheet
2010-2012 Microchip Technology Inc.
DS41440C-page 317
PIC16(L)F1825/1829
FIGURE 26-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 26-8:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON0
RXDTSEL
SDO1SEL
(1)
SS1SEL
(1)
—
T1GSEL
TXCKSEL
—
—
BAUDCON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RCREG
EUSART Receive Data Register
*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRGL
SPBRG<7:0>
*
SPBRGH
SPBRG<15:8>
*
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— Unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note
1:
PIC16(L)F1825 only.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)