Microchip Technology AC244045 Data Sheet
PIC16(L)F1825/1829
DS41440C-page 444
2010-2012 Microchip Technology Inc.
SSPOV Status Flag........................................................... 278
SSPxADD Register ........................................................... 292
SSPxCON1 Register......................................................... 289
SSPxCON2 Register......................................................... 290
SSPxCON3 Register......................................................... 291
SSPxMSK Register ........................................................... 292
SSPxSTAT Register.......................................................... 288
SSPxADD Register ........................................................... 292
SSPxCON1 Register......................................................... 289
SSPxCON2 Register......................................................... 290
SSPxCON3 Register......................................................... 291
SSPxMSK Register ........................................................... 292
SSPxSTAT Register.......................................................... 288
Accessing.................................................................... 43
Reset........................................................................... 45
Reset........................................................................... 45
Stack Overflow/Underflow................................................... 80
STATUS Register................................................................ 24
SUBWFB........................................................................... 345
STATUS Register................................................................ 24
SUBWFB........................................................................... 345
T
T1CON Register.......................................................... 31, 195
T1GCON Register............................................................. 196
T2CON Register.................................................................. 31
T4CON Register.................................................................. 39
T6CON Register.................................................................. 39
Temperature Indicator Module .......................................... 147
Thermal Considerations .................................................... 360
Timer0 ............................................................................... 183
T1GCON Register............................................................. 196
T2CON Register.................................................................. 31
T4CON Register.................................................................. 39
T6CON Register.................................................................. 39
Temperature Indicator Module .......................................... 147
Thermal Considerations .................................................... 360
Timer0 ............................................................................... 183
Associated Registers ................................................ 185
Operation .................................................................. 183
Specifications............................................................ 367
Operation .................................................................. 183
Specifications............................................................ 367
Associated registers.................................................. 197
Asynchronous Counter Mode ................................... 189
Asynchronous Counter Mode ................................... 189
Clock Source Selection............................................. 188
Interrupt..................................................................... 191
Operation .................................................................. 188
Operation During Sleep ............................................ 191
Oscillator ................................................................... 189
Prescaler................................................................... 189
Specifications............................................................ 367
Timer1 Gate
Interrupt..................................................................... 191
Operation .................................................................. 188
Operation During Sleep ............................................ 191
Oscillator ................................................................... 189
Prescaler................................................................... 189
Specifications............................................................ 367
Timer1 Gate
Timer2
Timers
Timer1
T1CON.............................................................. 195
T1GCON ........................................................... 196
T1GCON ........................................................... 196
Timer2/4/6
Timing Diagrams
A/D Conversion......................................................... 369
A/D Conversion (Sleep Mode) .................................. 369
Acknowledge Sequence ........................................... 280
Asynchronous Reception .......................................... 300
Asynchronous Transmission..................................... 296
Asynchronous Transmission (Back to Back) ............ 297
Auto Wake-up Bit (WUE) During Normal Operation . 312
Auto Wake-up Bit (WUE) During Sleep .................... 312
Automatic Baud Rate Calibration .............................. 310
Baud Rate Generator with Clock Arbitration ............. 273
BRG Reset Due to SDA Arbitration During Start
A/D Conversion (Sleep Mode) .................................. 369
Acknowledge Sequence ........................................... 280
Asynchronous Reception .......................................... 300
Asynchronous Transmission..................................... 296
Asynchronous Transmission (Back to Back) ............ 297
Auto Wake-up Bit (WUE) During Normal Operation . 312
Auto Wake-up Bit (WUE) During Sleep .................... 312
Automatic Baud Rate Calibration .............................. 310
Baud Rate Generator with Clock Arbitration ............. 273
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset Situations ........................................ 79
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 283
Bus Collision During a Stop Condition (Case 1) ....... 285
Bus Collision During a Stop Condition (Case 2) ....... 285
Bus Collision During Start Condition (SDA only) ...... 282
Bus Collision for Transmit and Acknowledge ........... 281
CLKOUT and I/O ...................................................... 363
Clock Synchronization .............................................. 270
Clock Timing............................................................. 362
Comparator Output ................................................... 175
Enhanced Capture/Compare/PWM (ECCP)............. 367
Fail-Safe Clock Monitor (FSCM)................................. 69
First Start Bit Timing ................................................. 274
Full-Bridge PWM Output........................................... 227
Half-Bridge PWM Output .................................. 225, 232
I
Bus Collision During a Stop Condition (Case 1) ....... 285
Bus Collision During a Stop Condition (Case 2) ....... 285
Bus Collision During Start Condition (SDA only) ...... 282
Bus Collision for Transmit and Acknowledge ........... 281
CLKOUT and I/O ...................................................... 363
Clock Synchronization .............................................. 270
Clock Timing............................................................. 362
Comparator Output ................................................... 175
Enhanced Capture/Compare/PWM (ECCP)............. 367
Fail-Safe Clock Monitor (FSCM)................................. 69
First Start Bit Timing ................................................. 274
Full-Bridge PWM Output........................................... 227
Half-Bridge PWM Output .................................. 225, 232
I
I
I
I
I
INT Pin Interrupt ......................................................... 88
Internal Oscillator Switch Timing ................................ 64
PWM Auto-shutdown................................................ 231
Internal Oscillator Switch Timing ................................ 64
PWM Auto-shutdown................................................ 231
PWM Direction Change ............................................ 228
PWM Direction Change at Near 100% Duty Cycle... 229
PWM Output (Active-High) ....................................... 223
PWM Output (Active-Low) ........................................ 224
Repeat Start Condition ............................................. 275
Reset Start-up Sequence ........................................... 81
Reset, WDT, OST and Power-up Timer ................... 364
Send Break Character Sequence............................. 313
SPI Master Mode (CKE = 1, SMP = 1) ..................... 372
SPI Mode (Master Mode).......................................... 247
SPI Slave Mode (CKE = 0) ....................................... 373
SPI Slave Mode (CKE = 1) ....................................... 373
Synchronous Reception (Master Mode, SREN) ....... 317
Synchronous Transmission ...................................... 315
Synchronous Transmission (Through TXEN) ........... 315
Timer0 and Timer1 External Clock ........................... 366
Timer1 Incrementing Edge ....................................... 191
Two Speed Start-up.................................................... 67
USART Synchronous Receive (Master/Slave) ......... 371
USART Synchronous Transmission (Master/Slave). 371
Wake-up from Interrupt............................................. 100
PWM Direction Change at Near 100% Duty Cycle... 229
PWM Output (Active-High) ....................................... 223
PWM Output (Active-Low) ........................................ 224
Repeat Start Condition ............................................. 275
Reset Start-up Sequence ........................................... 81
Reset, WDT, OST and Power-up Timer ................... 364
Send Break Character Sequence............................. 313
SPI Master Mode (CKE = 1, SMP = 1) ..................... 372
SPI Mode (Master Mode).......................................... 247
SPI Slave Mode (CKE = 0) ....................................... 373
SPI Slave Mode (CKE = 1) ....................................... 373
Synchronous Reception (Master Mode, SREN) ....... 317
Synchronous Transmission ...................................... 315
Synchronous Transmission (Through TXEN) ........... 315
Timer0 and Timer1 External Clock ........................... 366
Timer1 Incrementing Edge ....................................... 191
Two Speed Start-up.................................................... 67
USART Synchronous Receive (Master/Slave) ......... 371
USART Synchronous Transmission (Master/Slave). 371
Wake-up from Interrupt............................................. 100
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 361
Timing Requirements
Timing Requirements
I
TINLVLC Register............................................................. 138
TMR0 Register.................................................................... 31
TMR1H Register ................................................................. 31
TMR1L Register.................................................................. 31
TMR2 Register.................................................................... 31
TMR4 Register.................................................................... 39
TMR6 Register.................................................................... 39
TRIS.................................................................................. 346
TRISA Register........................................................... 32, 125
TRISB ............................................................................... 129
TMR0 Register.................................................................... 31
TMR1H Register ................................................................. 31
TMR1L Register.................................................................. 31
TMR2 Register.................................................................... 31
TMR4 Register.................................................................... 39
TMR6 Register.................................................................... 39
TRIS.................................................................................. 346
TRISA Register........................................................... 32, 125
TRISB ............................................................................... 129