Microchip Technology AC244045 Data Sheet

DS41440C-page 82

 2010-2012 Microchip Technology Inc.

Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. 

 show the Reset

conditions of these registers.

0

0

1

1

0

x

1

1

Power-on Reset

0

0

1

1

0

x

0

x

Illegal, TO is set on POR

0

0

1

1

0

x

x

0

Illegal, PD is set on POR

0

0

1

1

u

0

1

1

Brown-out Reset

u

u

u

u

u

u

0

u

WDT Reset 

u

u

u

u

u

u

0

0

WDT Wake-up from Sleep

u

u

u

u

u

u

1

0

Interrupt Wake-up from Sleep

u

u

0

u

u

u

u

u

MCLR Reset during normal operation

u

u

0

u

u

u

1

0

MCLR Reset during Sleep

u

u

u

0

u

u

u

u

RESET Instruction Executed

1

u

u

u

u

u

u

u

Stack Overflow Reset (STVREN = 1)

u

1

u

u

u

u

u

u

Stack Underflow Reset (STVREN = 1)

Power-on Reset

0000h

---1 1000

00-- 110x

MCLR Reset during normal operation

0000h

---u uuuu

uu-- 0uuu

MCLR Reset during Sleep

0000h

---1 0uuu

uu-- 0uuu

WDT Reset

0000h

---0 uuuu

uu-- uuuu

WDT Wake-up from Sleep

PC + 1

---0 0uuu

uu-- uuuu

Brown-out Reset

0000h

---1 1uuu

00-- 11u0

Interrupt Wake-up from Sleep

PC + 1

---1 0uuu

uu-- uuuu

RESET Instruction Executed 

0000h

---u uuuu

uu-- u0uu

Stack Overflow Reset (STVREN = 1)

0000h

---u uuuu

1u-- uuuu

Stack Underflow Reset (STVREN = 1)

0000h

---u uuuu

u1-- uuuu

Legend: u = unchanged,   x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on 

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.