Intel Mobile Celeron 440 TRAY M440 Leaflet
Product codes
TRAY M440
• Execute Disable Bit, when combined with a supporting operat-
ing system, allows memory to be marked as executable or
non-executable. If code attempts to run in non-executable
memory, the processor raises an error to the operating system.
This feature can prevent some classes of viruses or worms that
exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. Please refer to the IA-32
Intel® Architecture Software Developer’s Manual for more
details (
non-executable. If code attempts to run in non-executable
memory, the processor raises an error to the operating system.
This feature can prevent some classes of viruses or worms that
exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. Please refer to the IA-32
Intel® Architecture Software Developer’s Manual for more
details (
intel.com/products/processor/manuals/index.htm
).
• Embedded lifecycle support protects system investment by
enabling extended product availability for embedded, storage
and communications customers.
and communications customers.
• Along with a strong ecosystem of hardware and software
vendors, including members of the Intel® Communications Alliance
(
(
intel.com/go/ica
), Intel helps developers cost-effectively meet
design challenges and shorten time-to-market.
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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions
marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
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Copyright © 2007 Intel Corporation. All rights reserved.
Intel, the Intel logo, Intel. Leap ahead., Intel. Leap ahead. logo, Celeron, and Intel MMX are trademarks of Intel Corporation in the U.S. and other countries.
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Block diagram for the Intel® Celeron® M processor on 65nm
L2 Cache
APIC
Power
Management Logic
Core
Coordination Logic
Bus Interface
L1 Instruction and Data Cache
Th
er
m
al
Co
nt
ro
l
Execution Resources
Arch State
Intel® Celeron® M Processors on 65nm for Embedded Computing
Product Number
Core Speed
Front-Side
Bus Speed L2 Cache
Bus Speed L2 Cache
Thermal
Design Power VID
Design Power VID
Tjunction
Package
Intel® Celeron® M processor 550
∆
LF80537NE0411M
2.0 GHz
533 MHz
1 MB
31 W
1.25V
0-100˚ C
478 µFC-PGA
LE80537NE0411M
2.0 GHz
533 MHz
1 MB
31 W
1.25V
0-100˚ C
479 µFC-BGA
Intel® Celeron® M processor 530
∆
LF80537NE0301M
1.73 GHz
533 MHz
1 MB
31 W
1.25V
0-100˚ C
478 µFC-PGA
LE80537NE0301M
1.73 GHz
533 MHz
1 MB
31 W
1.25V
0-100˚ C
479 µFC-BGA
Intel® Celeron® M processor 440
∆
LF80538NE0361M
1.86 GHz
533 MHz
1 MB
27 W
1.26 V
0-100˚ C
478 µFC-PGA
LE80538NE0361M
1.86 GHz
533 MHz
1 MB
27 W
1.26 V
0-100˚ C
479 µFC-BGA
Intel® Celeron® M processor Ultra Low Voltage 423
∆
LE80538VE0041M
1.06 GHz
533 MHz
1 MB
5.5 W
0.94 V
0-100˚ C
479 µFC-BGA
∆
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families.
See http://www.intel.com/products/processor_number for details.
Product Highlights (continued)