Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 119

U-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

—

ADIF

RC1IF

TX1IF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’. 

bit 6

ADIF: A/D Converter Interrupt Flag bit 

1

 = An A/D conversion completed (must be cleared by software) 

0

 = The A/D conversion is not complete or has not been started

bit 5

RC1IF: EUSART1 Receive Interrupt Flag bit 

1

 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 

0

 = The EUSART1 receive buffer is empty 

bit 4

TX1IF: EUSART1 Transmit Interrupt Flag bit 

1

 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 

0

 = The EUSART1 transmit buffer is full 

bit 3

SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 

1

 = The transmission/reception is complete (must be cleared by software)

0

 = Waiting to transmit/receive

bit 2

CCP1IF: CCP1 Interrupt Flag bit 

Capture mode: 
1

 = A TMR1 register capture occurred (must be cleared by software) 

0

 = No TMR1 register capture occurred 

Compare mode: 
1

 = A TMR1 register compare match occurred (must be cleared by software) 

0

 = No TMR1 register compare match occurred

PWM mode: 
Unused in this mode

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1

 = TMR2 to PR2 match occurred (must be cleared by software) 

0

 = No TMR2 to PR2 match occurred 

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit 

1

 = TMR1 register overflowed (must be cleared by software)

0

 = TMR1 register did not overflow

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Global Interrupt Enable bit, GIE/
GIEH of the INTCON register. 

User software should ensure the appro-
priate interrupt flag bits are cleared prior
to enabling an interrupt and after servic-
ing that interrupt.