Microchip Technology MA160014 Data Sheet

Page of 560
 2010-2012 Microchip Technology Inc.
DS41412F-page 133
PIC18(L)F2X/4XK22
TABLE 9-1:
REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 
on Page
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1 INTEDG2
TMR0IP
RBIP
INTCON3
INT2IP
INT1IP
INT2IE
INT1IE
INT2IF
INT1IF
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP TMR5GIP TMR3GIP
TMR1GIP
IPR4
CCP5IP
CCP4IP
CCP3IP
IPR5
TMR6IP
TMR5IP
TMR4IP
PIE1
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE TMR5GIE TMR3GIE
TMR1GIE
PIE4
CCP5IE
CCP4IE
CCP3IE
PIE5
TMR6IE
TMR5IE
TMR4IE
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF TMR5GIF
TMR3GIF
TMR1GIF
PIR4
CCP5IF
CCP4IF
CCP3IF
PIR5
TMR6IF
TMR5IF
TMR4IF
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RCON
IPEN
SBOREN
RI
TO
PD
POR
BOR
Legend:  — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.
TABLE 9-2:
CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 
on Page
CONFIG3H
MCLRE
P2BMX
T3CMX
HFOFST
CCP3MX
PBADEN
CCP2MX
CONFIG4L
DEBUG
XINST
LVP
STRVEN
Legend:  — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.