Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 141

A mismatch condition will continue to set the RBIF flag bit.
Reading or writing PORTB will end the mismatch
condition and allow the RBIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RBIF flag will continue to be set if a mismatch is present.   

The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.

10.3.3

ALTERNATE FUNCTIONS

PORTB is multiplexed with several peripheral functions
(

). The pins have TTL input buffers. Some of

these pin functions can be relocated to alternate pins
using the Control fuse bits in CONFIG3H. RB5 is the
default pin for P2B (28-pin devices). Clearing the
P2BMX bit moves the pin function to RC0. RB5 is also
the default pin for the CCP3/P3A peripheral pin. Clear-
ing the CCP3MX bit moves the pin function to the RC6
pin (28-pin devices) or RE0 (40/44-pin devices).

Two other pin functions, T3CKI and CCP2/P2A, can be
relocated from their default pins to PORTB pins by
clearing the control fuses in CONFIG3H. Clearing
T3CMX and CCP2MX moves the pin functions to RB5
and RB3, respectively.

If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.

RB0/INT0/CCP4/
FLT0/SRI/SS2/
AN12

RB0

0

0

O

DIG

LATB<0> data output; not affected by analog input.

1

0

I

TTL

PORTB<0> data input; disabled when analog input 
enabled.

INT0

1

0

I

ST

External interrupt 0.

CCP4

0

0

O

DIG

Compare 4 output/PWM 4 output.

1

0

I

ST

Capture 4 input.

FLT0

1

0

I

ST

PWM Fault input for ECCP auto-shutdown.

SRI

1

0

I

ST

SR latch input.

SS2

1

0

I

TTL

SPI slave select input (MSSP2).

AN12

1

1

I

AN

Analog input 12.

RB1/INT1/P1C/
SCK2/SCL2/
C12IN3-/AN10

RB1

0

0

O

DIG

LATB<1> data output; not affected by analog input.

1

0

I

TTL

PORTB<1> data input; disabled when analog input 
enabled.

INT1

1

0

I

ST

External Interrupt 1.

P1C

0

0

O

DIG

Enhanced CCP1 PWM output 3.

SCK2

0

0

O

DIG

MSSP2 SPI Clock output.

1

0

I

ST

MSSP2 SPI Clock input.

SCL2

0

0

O

DIG

MSSP2  I

2

C

TM

 

Clock output.

1

0

I

I

2

C

MSSP2 I

2

C

TM

 

Clock input.

C12IN3-

1

1

I

AN

Comparators C1 and C2 inverting input.

AN10

1

1

I

AN

Analog input 10.

AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = 
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I

2

C

TM

 = 

Schmitt Trigger input with I

2

C.

Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and 
CCP2MX are set.

Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and 
CCP2MX are clear.

Function on PORTD and PORTE for PIC18(L)F4XK22 devices.