Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 19
PIC18(L)F2X/4XK22
25
22
RB4/IOC0/P1D/T5G/AN11
RB4
I/O
TTL
Digital I/O.
IOC0
I
TTL
Interrupt-on-change pin.
P1D
O
CMOS
Enhanced CCP1 PWM output.
T5G
I
ST
Timer5 external clock gate input.
AN11
I
Analog
Analog input 11.
26
23
RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13
RB5
I/O
TTL
Digital I/O.
IOC1
I
TTL
Interrupt-on-change pin.
P2B
(1)
O
CMOS
Enhanced CCP2 PWM output.
P3A
(1)
O
CMOS
Enhanced CCP3 PWM output.
CCP3
(1)
I/O
ST
Capture 3 input/Compare 3 output/PWM 3 output.
T3CKI
(2)
I
ST
Timer3 clock input.
T1G
I
ST
Timer1 external clock gate input.
AN13
I
Analog
Analog input 13.
27
24
RB6/IOC2/TX2/CK2/PGC
RB6
I/O
TTL
Digital I/O.
IOC2
I
TTL
Interrupt-on-change pin.
TX2
O
—
EUSART asynchronous transmit.
CK2
I/O
ST
EUSART synchronous clock (see related RXx/DTx).
PGC
I/O
ST
In-Circuit Debugger and ICSP™ programming clock pin.
28
25
RB7/IOC3/RX2/DT2/PGD
RB7
I/O
TTL
Digital I/O.
IOC3
I
TTL
Interrupt-on-change pin.
RX2
I
ST
EUSART asynchronous receive.
DT2
I/O
ST
EUSART synchronous data (see related TXx/CKx).
PGD
I/O
ST
In-Circuit Debugger and ICSP™ programming data pin.
11
8
RC0/P2B/T3CKI/T3G/T1CKI/SOSCO
RC0
I/O
TTL
Digital I/O.
P2B
(2)
O
CMOS
Enhanced CCP1 PWM output.
T3CKI
(1)
I
ST
Timer3 clock input.
T3G
I
ST
Timer3 external clock gate input.
T1CKI
I
ST
Timer1 clock input.
SOSCO
O
—
Secondary oscillator output.
12
9
RC1/P2A/CCP2/SOSCI
RC1
I/O
TTL
Digital I/O.
P2A
O
CMOS
Enhanced CCP2 PWM output.
CCP2
(1)
I/O
ST
Capture 2 input/Compare 2 output/PWM 2 output.
SOSCI
I
Analog
Secondary oscillator input.
TABLE 1-2:
PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin
Type
Buffer
Type
Description
PDIP,
SOIC
SOIC
QFN,
UQFN
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
CCP2MX are clear.