Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 190
2010-2012 Microchip Technology Inc.
14.4
PWM (Enhanced Mode)
The enhanced PWM function described in this section is
available for CCP modules ECCP1, ECCP2 and
ECCP3, with any differences between modules noted.
available for CCP modules ECCP1, ECCP2 and
ECCP3, with any differences between modules noted.
The enhanced PWM mode generates a Pulse-Width
Modulation (PWM) signal on up to four different output
pins with up to ten bits of resolution. The period, duty
cycle, and resolution are controlled by the following
registers:
Modulation (PWM) signal on up to four different output
pins with up to ten bits of resolution. The period, duty
cycle, and resolution are controlled by the following
registers:
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
The ECCP modules have the following additional PWM
registers which control Auto-shutdown, Auto-restart,
Dead-band Delay and PWM Steering modes:
registers which control Auto-shutdown, Auto-restart,
Dead-band Delay and PWM Steering modes:
• ECCPxAS registers
• PSTRxCON registers
• PWMxCON registers
The enhanced PWM module can generate the following
five PWM Output modes:
five PWM Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
• Single PWM with PWM Steering mode
To select an Enhanced PWM Output mode, the
PxM<1:0> bits of the CCPxCON register must be
configured appropriately.
PxM<1:0> bits of the CCPxCON register must be
configured appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
designated PxA, PxB, PxC and PxD. The polarity of the
PWM pins is configurable and is selected by setting the
CCPxM bits in the CCPxCON register appropriately.
shows an example of a simplified block
diagram of the Enhanced PWM module.
shows the pin assignments for various
Enhanced PWM modes.
FIGURE 14-5:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
3: Any pin not used in the enhanced PWM
mode is available for alternate pin
functions, if applicable.
functions, if applicable.
4: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits
until the start of a new PWM period
before generating a PWM signal.
first enabled, the ECCP module waits
until the start of a new PWM period
before generating a PWM signal.
CCPRxL
CCPRxH (Slave)
Comparator
TMRx
Comparator
PRx
(1)
R
Q
S
Duty Cycle Registers
DCxB<1:0>
Clear Timer,
toggle PWM pin and
latch duty cycle
toggle PWM pin and
latch duty cycle
Note
1:
The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time
base.
base.
2:
PxC and PxD are not available on half-bridge ECCP modules.
TRISx
CCPx/PxA
TRISx
PxB
TRISx
PxC
(2)
TRISx
PxD
(2)
Output
Controller
PxM<1:0>
2
CCPxM<3:0>
4
PWMxCON
CCPx/PxA
PxB
PxC
PxD