Microchip Technology MA160014 Data Sheet

Page of 560
PIC18(L)F2X/4XK22
DS41412F-page 22
 2010-2012 Microchip Technology Inc.
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RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4
RA5
I/O
TTL
Digital I/O.
C2OUT
O
CMOS
Comparator C2 output.
SRNQ
O
TTL
SR latch Q output.
SS1
I
TTL
SPI slave select input (MSSP1).
HLVDIN
I
Analog High/Low-Voltage Detect input.
AN4
I
Analog Analog input 4.
14
31
33
29
RA6/CLKO/OSC2
RA6
I/O
TTL
Digital I/O.
CLKO
O
In RC mode, OSC2 pin outputs CLKOUT which 
has 1/4 the frequency of OSC1 and denotes the 
instruction cycle rate.
OSC2
O
Oscillator crystal output. Connects to crystal or 
resonator in Crystal Oscillator mode.
13
30
32
28
RA7/CLKI/OSC1
RA7
I/O
TTL
Digital I/O.
CLKI
I
CMOS
External clock source input. Always associated 
with pin function OSC1.
OSC1
I
ST
Oscillator crystal input or external clock source 
input ST buffer when configured in RC mode; 
CMOS otherwise.
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8
9
8
RB0/INT0/FLT0/SRI/AN12
RB0
I/O
TTL
Digital I/O.
INT0
I
ST
External interrupt 0.
FLT0
I
ST
PWM Fault input for ECCP Auto-Shutdown.
SRI
I
ST
SR latch input.
AN12
I
Analog Analog input 12.
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9
10
9
RB1/INT1/C12IN3-/AN10
RB1
I/O
TTL
Digital I/O.
INT1
I
ST
External interrupt 1.
C12IN3-
I
Analog Comparators C1 and C2 inverting input.
AN10
I
Analog Analog input 10.
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10
11
10
RB2/INT2/CTED1/AN8
RB2
I/O
TTL
Digital I/O.
INT2
I
ST
External interrupt 2.
CTED1
I
ST
CTMU Edge 1 input.
AN8
I
Analog Analog input 8.
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11
12
11
RB3/CTED2/P2A/CCP2/C12IN2-/AN9
RB3
I/O
TTL
Digital I/O.
CTED2
I
ST
CTMU Edge 2 input.
P2A
(2)
O
CMOS
Enhanced CCP2 PWM output.
CCP2
(2)
I/O
ST
Capture 2 input/Compare 2 output/PWM 2 output.
C12IN2-
I
Analog Comparators C1 and C2 inverting input.
AN9
I
Analog Analog input 9.
TABLE 1-3:
PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Name
Pin 
Type
Buffer 
Type
Description
PDIP
TQFP
QFN
UQFN
Legend:
TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;   
I = Input; O = Output; P = Power.
Note
1:
Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2:
Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.