Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 234
2010-2012 Microchip Technology Inc.
15.5.3.3
7-bit Transmission with Address
Hold Enabled
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1.
Bus starts Idle.
2.
Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is
generated.
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is
generated.
4.
Slave software clears SSPxIF.
5.
Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6.
Slave reads the address value from the SSPxBUF
register clearing the BF bit.
register clearing the BF bit.
7.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
8.
Slave sets the CKP bit releasing SCLx.
9.
Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCLx pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte
transmitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Stop and end the communication.
Note: SSPxBUF cannot be loaded until after the
ACK.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCLx
line to receive a Stop.
line to receive a Stop.