Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 275
PIC18(L)F2X/4XK22
FIGURE 16-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RXx/DTx pin
Reg
Rcv Buffer Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREGx
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
RCREGx
Stop
bit
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
word, causing the OERR (overrun) bit to be set.
RCIDL
TABLE 16-2:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
PMD0
UART2MD
UART1MD TMR6MD TMR5MD TMR4MD
TMR3MD
TMR2MD
TMR1MD
RCREG1
EUSART1 Receive Register
—
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG2
EUSART2 Receive Register
—
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRG1
EUSART1 Baud Rate Generator, Low Byte
—
SPBRGH1
EUSART1 Baud Rate Generator, High Byte
—
SPBRG2
EUSART2 Baud Rate Generator, Low Byte
—
SPBRGH2
EUSART2 Baud Rate Generator, High Byte
—
TRISB
(2)
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TRISD
(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
Note
1: PIC18(L)F4XK22 devices.
2: PIC18(L)F2XK22 devices.