Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 280
2010-2012 Microchip Technology Inc.
16.4
EUSART Baud Rate Generator
(BRG)
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCONx register selects 16-bit
mode.
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCONx register selects 16-bit
mode.
The SPBRGHx:SPBRGx register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXSTAx register and the BRG16 bit of the BAUDCONx
register. In Synchronous mode, the BRGH bit is ignored.
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXSTAx register and the BRG16 bit of the BAUDCONx
register. In Synchronous mode, the BRGH bit is ignored.
baud rate.
provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in
Asynchronous modes have been computed for your
convenience and are shown in
. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGHx, SPBRGx
register pair causes the BRG timer to be reset (or
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.
register pair causes the BRG timer to be reset (or
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 16-1:
CALCULATING BAUD
RATE ERROR
RATE ERROR
For a device with F
OSC
of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGHx:SPBRGx:
X
F
O S C
Desired Baud Rate
---------------------------------------------
64
---------------------------------------------
1
–
=
Desired Baud Rate
F
OS C
64 [SPBRGHx:SPBRGx]
1
+
--------------------------------------------------------------------------
=
16000000
9600
------------------------
64
------------------------
1
–
=
25.042
25
=
=
Calculated Baud Rate
16000000
64 25
1
+
---------------------------
=
9615
=
Error
Calc. Baud Rate
Desired Baud Rate
–
Desired Baud Rate
--------------------------------------------------------------------------------------------
=
9615
9600
–
9600
----------------------------------
0.16%
=
=
TABLE 16-3:
BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
8-bit/Asynchronous
F
OSC
/[64 (n+1)]
0
0
1
8-bit/Asynchronous
F
OSC
/[16 (n+1)]
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
F
OSC
/[4 (n+1)]
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
Legend:
x
= Don’t care, n = value of SPBRGHx, SPBRGx register pair.