Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 284
2010-2012 Microchip Technology Inc.
16.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
BRG is reversed. Rather than the BRG clocking the
incoming RXx signal, the RXx signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
). While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPBRGx begins
counting up using the BRG counter clock as shown in
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPBRGx begins
counting up using the BRG counter clock as shown in
. The fifth rising edge will occur on the RXx/
DTx pin at the end of the eighth bit period. At that time,
an accumulated value totaling the proper BRG period
is left in the SPBRGHx:SPBRGx register pair, the
ABDEN bit is automatically cleared, and the RCxIF
interrupt flag is set. A read operation on the RCREGx
needs to be performed to clear the RCxIF interrupt.
RCREGx content should be discarded. When
calibrating for modes that do not use the SPBRGHx
register the user can verify that the SPBRGx register
did not overflow by checking for 00h in the SPBRGHx
register.
an accumulated value totaling the proper BRG period
is left in the SPBRGHx:SPBRGx register pair, the
ABDEN bit is automatically cleared, and the RCxIF
interrupt flag is set. A read operation on the RCREGx
needs to be performed to clear the RCxIF interrupt.
RCREGx content should be discarded. When
calibrating for modes that do not use the SPBRGHx
register the user can verify that the SPBRGx register
did not overflow by checking for 00h in the SPBRGHx
register.
. During ABD,
both the SPBRGHx and SPBRGx registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGHx
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGHx
and SPBRGx registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
FIGURE 16-6:
AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
following the Break character (see
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the auto-
baud counter starts counting at one. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract one
from the SPBRGHx:SPBRGx register pair.
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract one
from the SPBRGHx:SPBRGx register pair.
TABLE 16-6:
BRG COUNTER CLOCK
RATES
RATES
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
F
OSC
/64
F
OSC
/512
0
1
F
OSC
/16
F
OSC
/128
1
0
F
OSC
/16
F
OSC
/128
1
1
F
OSC
/4
F
OSC
/32
Note:
During the ABD sequence, SPBRGx and
SPBRGHx registers are both used as a
16-bit counter, independent of BRG16
setting.
SPBRGHx registers are both used as a
16-bit counter, independent of BRG16
setting.
BRG Value
RXx/DTx pin
ABDEN bit
RCxIF bit
bit 0
bit 1
(Interrupt)
Read
RCREGx
BRG Clock
Start
Auto Cleared
Set by User
XXXXh
0000h
Edge #1
bit 2
bit 3
Edge #2
bit 4
bit 5
Edge #3
bit 6
bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPBRGx
XXh
1Ch
SPBRGHx
XXh
00h
RCIDL