Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 298
2010-2012 Microchip Technology Inc.
17.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
17.1.1
PORT CONFIGURATION
The ANSELx and TRISx registers configure the A/D
port pins. Any port pin needed as an analog input
should have its corresponding ANSx bit set to disable
the digital input buffer and TRISx bit set to disable the
digital output driver. If the TRISx bit is cleared, the
digital output level (V
port pins. Any port pin needed as an analog input
should have its corresponding ANSx bit set to disable
the digital input buffer and TRISx bit set to disable the
digital output driver. If the TRISx bit is cleared, the
digital output level (V
OH
or V
OL
) will be converted.
The A/D operation is independent of the state of the
ANSx bits and the TRIS bits.
ANSx bits and the TRIS bits.
17.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to
starting the next conversion. Refer to
for more information.
17.1.3
ADC V
OLTAGE REFERENCE
The PVCFG<1:0> and NVCFG<1:0> bits of the
ADCON1 register provide independent control of the
positive and negative voltage references.
ADCON1 register provide independent control of the
positive and negative voltage references.
The positive voltage reference can be:
• V
DD
• the fixed voltage reference (FVR BUF2)
• an external voltage source (V
REF
+)
The negative voltage reference can be:
• V
SS
• an external voltage source (V
REF
-)
17.1.4
SELECTING AND CONFIGURING
ACQUISITION TIME
ACQUISITION TIME
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
acquisition time that occurs each time the GO/DONE
bit is set.
Acquisition time is set with the ACQT<2:0> bits of the
ADCON2 register. Acquisition delays cover a range of
2 to 20 T
ADCON2 register. Acquisition delays cover a range of
2 to 20 T
AD
. When the GO/DONE bit is set, the A/D
module continues to sample the input for the selected
acquisition time, then automatically begins a
conversion. Since the acquisition time is programmed,
there is no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
acquisition time, then automatically begins a
conversion. Since the acquisition time is programmed,
there is no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
ACQT<2:0> = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT<2:0> bits and
is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. When an acquisition time is programmed, there
is no indication of when the acquisition time ends and
the conversion begins.
Note 1: When reading the PORT register, all pins
with their corresponding ANSx bit set
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
read as cleared (a low level). However,
analog conversion of pins configured as
digital inputs (ANSx bit cleared and
TRISx bit set) will be accurately
converted.
2: Analog levels on any pin with the corre-
sponding ANSx bit cleared may cause
the digital input buffer to consume current
out of the device’s specification limits.
the digital input buffer to consume current
out of the device’s specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by
controlling how the bits in ANSELB are
reset.
reset as analog or digital pins by
controlling how the bits in ANSELB are
reset.