Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 301
PIC18(L)F2X/4XK22
17.2
ADC Operation
17.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will, depend-
ing on the ACQT bits of the ADCON2 register, either
immediately start the Analog-to-Digital conversion or
start an acquisition delay followed by the Analog-to-
Digital conversion.
shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
are cleared. A conversion is started after the following
instruction to allow entry into SLEEP mode before the
conversion begins.
shows the operation of the A/D converter
after the GO bit has been set and the ACQT<2:0> bits
are set to ‘010’ which selects a 4 T
are set to ‘010’ which selects a 4 T
AD
acquisition time
before the conversion starts.
FIGURE 17-3:
A/D CONVERSION T
AD
CYCLES (A
CQT
<2:0> = 000, T
ACQ
= 0)
FIGURE 17-4:
A/D CONVERSION T
AD
CYCLES (A
CQT
<2:0> = 010, T
ACQ
= 4 T
AD
)
Note:
T
AD
1 T
AD
2 T
AD
3 T
AD
4 T
AD
5 T
AD
6 T
AD
7 T
AD
8
T
AD
11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
T
AD
9 T
AD
10
T
CY
- T
AD
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
On the following cycle:
2 T
AD
Discharge
1
2
3
4
5
6
7
8
11
Set GO bit
(Holding capacitor is disconnected from analog input)
9
10
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
acquiring input)
T
ACQT
Cycles
T
AD
Cycles
Automatic
Acquisition
Time
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
2 T
AD
Discharge