Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 332
2010-2012 Microchip Technology Inc.
19.6
Creating a Delay with the CTMU
Module
Module
A unique feature on board the CTMU module is its
ability to generate system clock independent output
pulses based on an external capacitor value. This is
accomplished using the internal comparator voltage
reference module, Comparator 2 input pin and an
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit.
ability to generate system clock independent output
pulses based on an external capacitor value. This is
accomplished using the internal comparator voltage
reference module, Comparator 2 input pin and an
external capacitor. The pulse is output onto the CTPLS
pin. To enable this mode, set the TGEN bit.
See
for an example circuit. C
PULSE
is
chosen by the user to determine the output pulse width
on CTPLS. The pulse width is calculated by
T = (C
on CTPLS. The pulse width is calculated by
T = (C
PULSE
/I)*V, where I is known from the current
source measurement step (
) and V is the internal reference
voltage (CV
REF
).
An example use of this feature is for interfacing with
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
on CTPLS will vary. The CTPLS output pin can be con-
nected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
variable capacitive-based sensors, such as a humidity
sensor. As the humidity varies, the pulse width output
on CTPLS will vary. The CTPLS output pin can be con-
nected to an input capture pin and the varying pulse
width is measured to determine the humidity in the
application.
Follow these steps to use this feature:
1.
Initialize Comparator 2.
2.
Initialize the comparator voltage reference.
3.
Initialize the CTMU and enable time delay
generation by setting the TGEN bit.
generation by setting the TGEN bit.
4.
Set EDG1STAT.
5.
When C
PULSE
charges to the value of the voltage
reference trip point, an output pulse is generated
on CTPLS.
on CTPLS.
FIGURE 19-4:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
DELAY GENERATION
19.7
Operation During Sleep/Idle
Modes
Modes
19.7.1
SLEEP MODE AND DEEP SLEEP
MODES
MODES
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
19.7.2
IDLE MODE
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. If the
module is performing an operation when Idle mode is
invoked, in this case, the results will be similar to those
with Sleep mode.
19.8
CTMU Peripheral Module Disable
(PMD)
(PMD)
When this peripheral is not used, the Peripheral
Module Disable bit can be set to disconnect all clock
sources to the module, reducing power consumption to
an absolute minimum. See
Module Disable bit can be set to disconnect all clock
sources to the module, reducing power consumption to
an absolute minimum. See
.
C2
CV
REF
CTPLS
PIC18(L)FXXK22 Device
Current Source
Comparator
CTMU
CTED1
C12IN1-
C
PULSE
EDG1