Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 337

The module consists of a single SR latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR latch module includes the following features:

• Programmable input selection

• SR latch output is available internally/externally

• Selectable Q and Q output

• Firmware Set and Reset

The SR latch can be used in a variety of analog
applications, including oscillator circuits, one-shot
circuit, hysteretic controllers, and analog timing
applications.

The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. The latch can be set or reset by:

• Software control (SRPS and SRPR bits)

• Comparator C1 output (sync_C1OUT)

• Comparator C2 output (sync_C2OUT)

• SRI  Pin

• Programmable clock (DIVSRCLK)

The SRPS and the SRPR bits of the SRCON0 register
may be used to set or reset the SR latch, respectively.
The latch is Reset-dominant. Therefore, if both Set and
Reset inputs are high, the latch will go to the Reset
state. Both the SRPS and SRPR bits are self resetting
which means that a single write to either of the bits is
all that is necessary to complete a latch Set or Reset
operation.

The output from Comparator C1 or C2 can be used as
the Set or Reset inputs of the SR latch. The output of
either Comparator can be synchronized to the Timer1
clock source. See 

 and 

 for more information.

An external source on the SRI pin can be used as the
Set or Reset inputs of the SR latch.

An internal clock source, DIVSRCLK, is available and it
can periodically set or reset the SR latch. The
SRCLK<2:0> bits in the SRCON0 register are used to
select the clock source period. The SRSCKE and
SRRCKE bits of the SRCON1 register enable the clock
source to set or reset the SR latch, respectively.

The SRQEN and SRNQEN bits of the SRCON0
register control the Q and Q latch outputs. Both of the
SR latch outputs may be directly output to I/O pins at
the same time. Control is determined by the state of bits
SRQEN and SRNQEN in the SRCON0 register.

The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver. 

The DIVSRCLK clock signal is generated from the
peripheral clock which is pre-scaled by a value
determined by the SRCLK<2:0> bits. See 

and 

 for additional detail.

Upon any device Reset, the SR latch is not initialized,
and the SRQ and SRNQ outputs are unknown. The
user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.