Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 369
PIC18(L)F2X/4XK22
24.5.1
PROGRAM MEMORY
CODE PROTECTION
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In Normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit cleared to ‘0’, a table READ instruction that executes
from within that block is allowed to read. A table read
instruction that executes from a location outside of that
block is not allowed to read and will result in reading ‘0’s.
Figures
block is not allowed to read and will result in reading ‘0’s.
Figures
through
illustrate table write and table
read protection.
FIGURE 24-3:
TABLE WRITE (WRTn) DISALLOWED
Note:
Code protection bits may only be written
to a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP™ or an external
programmer.
to a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP™ or an external
programmer.
000000h
0007FFh
000800h
000800h
001FFFh
002000h
002000h
003FFFh
004000h
004000h
005FFFh
006000h
006000h
007FFFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
TBLWT*
TBLPTR = 0008FFh
PC = 001FFEh
TBLWT*
PC = 005FFEh
Register Values
Program Memory
Configuration Bit Settings
Results: All table writes disabled to Blockn whenever WRTn = 0
.