Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 373
PIC18(L)F2X/4XK22
25.0
INSTRUCTION SET SUMMARY
PIC18(L)F2X/4XK22 devices incorporate the standard
set of 75 PIC18 core instructions, as well as an extended
set of eight new instructions, for the optimization of code
that is recursive or that utilizes a software stack. The
extended set is discussed later in this section.
set of 75 PIC18 core instructions, as well as an extended
set of eight new instructions, for the optimization of code
that is recursive or that utilizes a software stack. The
extended set is discussed later in this section.
25.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC
enhancements to the previous PIC
®
MCU instruction
sets, while maintaining an easy migration from these
PIC
PIC
®
MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in
lists
byte-oriented, bit-oriented, literal and control
operations.
operations.
shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
The file register (specified by ‘f’)
2.
The destination of the result (specified by ‘d’)
3.
The accessed memory (specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
register is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the opera-
tion is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
The file register (specified by ‘f’)
2.
The bit in the file register (specified by ‘b’)
3.
The accessed memory (specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.
The literal instructions may use some of the following
operands:
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the four MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the four MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1
s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2
an instruction, the instruction execution time is 2
s.
Two-word branch instructions (if true) would take 3
s.
shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
to represent a hexadecimal number.
The Instruction Set Summary, shown in
lists the standard instructions recognized by the
Microchip Assembler (MPASM
Microchip Assembler (MPASM
TM
).
provides
a description of each instruction.