Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 413

             

    

       

      

      

       

Syntax:

TSTFSZ f {,a}

Operands:

0 

 f  255

a 

 [0,1]

Operation:

skip if f = 0

Status Affected:

None

Encoding:

0110

011a

ffff

ffff

Description:

If ‘f’ = 0, the next instruction fetched 
during the current instruction execution 
is discarded and a NOP is executed, 
making this a two-cycle instruction. 
If ‘a’ is ‘0’, the Access Bank is selected. 
If ‘a’ is ‘1’, the BSR is used to select the 
GPR bank.
If ‘a’ is ‘0’ and the extended instruction 
set is enabled, this instruction operates 
in Indexed Literal Offset Addressing 
mode whenever f 

95 (5Fh). See 

 for details.

Words:

1

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process 

Data

No 

operation

If skip:

Q1

Q2

Q3

Q4

No 

operation

No 

operation

No 

operation

No 

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No 

operation

No 

operation

No 

operation

No 

operation

No 

operation

No 

operation

No 

operation

No 

operation

Example:

HERE    TSTFSZ  CNT, 1

NZERO   :

ZERO    :

Before Instruction

PC =

Address (HERE)

After Instruction

If CNT

=

00h,

PC = 

Address (ZERO)

If CNT



00h,

PC = 

Address 

(NZERO)

Syntax:

XORLW   k

Operands:

0 

k 255

Operation:

(W) .XOR. k 

W

Status Affected:

N, Z

Encoding:

0000

1010

kkkk

kkkk

Description:

The contents of W are XORed with 
the 8-bit literal ‘k’. The result is placed 
in W.

Words:

1

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process 

Data

Write to W

Example:

XORLW

 0AFh

Before Instruction

W

=

B5h

After Instruction

W

=

1Ah