Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 55

PIC18(L)F2X/4XK22

3.6

Selective Peripheral Module
Control

Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, con-
sume power. There may be cases where the applica-
tion needs what IDLE mode does not provide: the
allocation of power resources to the CPU processing
with minimal power consumption from the peripherals.
PIC18(L)F2X/4XK22 family devices address this
requirement by allowing peripheral modules to be
selectively disabled, reducing or eliminating their
power consumption. This can be done with control bits
in the Peripheral Module Disable (PMD) registers.
These bits generically named XXXMD are located in
control registers PMD0, PMD1 or PMD2.

Setting the PMD bit for a module disables all clock
sources to that module, reducing its power
consumption to an absolute minimum. In this state,
power to the control and status registers associated
with the peripheral is removed. Writes to these
registers have no effect and read values are invalid.
Clearing a set PMD bit restores power to the
associated control and status registers, thereby setting
those registers to their default values.

3.7

Register Definitions: Peripheral Module Disable

REGISTER 3-1:

PMD0: PERIPHERAL MODULE DISABLE REGISTER 0

R/W-0

UART2MD

UART1MD

TMR6MD

TMR5MD

TMR4MD

TMR3MD

TMR2MD

TMR1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

UART2MD: UART2 Peripheral Module Disable Control bit