Microchip Technology MA160014 Data Sheet
PIC18(L)F2X/4XK22
DS41412F-page 554
2010-2012 Microchip Technology Inc.
Timers
Timer1/3/5
TxCON ............................................................. 172
TxGCON .......................................................... 173
TxGCON .......................................................... 173
Timer2/4/6
Timing Diagrams
A/D Conversion ........................................................ 464
Acknowledge Sequence .......................................... 250
Asynchronous Reception ......................................... 275
Asynchronous Transmission .................................... 270
Asynchronous Transmission (Back to Back) ........... 271
Auto Wake-up Bit (WUE) During Normal Operation 286
Auto Wake-up Bit (WUE) During Sleep ................... 286
Automatic Baud Rate Calculator .............................. 285
Baud Rate Generator with Clock Arbitration ............ 243
BRG Reset Due to SDA Arbitration During Start
Acknowledge Sequence .......................................... 250
Asynchronous Reception ......................................... 275
Asynchronous Transmission .................................... 270
Asynchronous Transmission (Back to Back) ........... 271
Auto Wake-up Bit (WUE) During Normal Operation 286
Auto Wake-up Bit (WUE) During Sleep ................... 286
Automatic Baud Rate Calculator .............................. 285
Baud Rate Generator with Clock Arbitration ............ 243
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR) ........................................... 452
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) .... 254
Bus Collision During a Stop Condition (Case 1) ...... 256
Bus Collision During a Stop Condition (Case 2) ...... 256
Bus Collision During Start Condition (SDA only) ..... 253
Bus Collision for Transmit and Acknowledge ........... 252
Capture/Compare/PWM (CCP) ................................ 454
CLKO and I/O .......................................................... 451
Clock Synchronization ............................................. 240
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 311
EUSART Synchronous Receive (Master/Slave) ...... 463
EUSART Synchronous Transmission
Bus Collision During a Stop Condition (Case 1) ...... 256
Bus Collision During a Stop Condition (Case 2) ...... 256
Bus Collision During Start Condition (SDA only) ..... 253
Bus Collision for Transmit and Acknowledge ........... 252
Capture/Compare/PWM (CCP) ................................ 454
CLKO and I/O .......................................................... 451
Clock Synchronization ............................................. 240
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 311
EUSART Synchronous Receive (Master/Slave) ...... 463
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 455
Example SPI Master Mode (CKE = 1) ..................... 456
Example SPI Master Mode Timing .......................... 455
Example SPI Slave Mode (CKE = 0) ....................... 457
Example SPI Slave Mode (CKE = 1) ....................... 458
External Clock (All Modes except PLL) .................... 449
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 244
Full-Bridge PWM Output .......................................... 195
Half-Bridge PWM Output ................................. 193, 199
High/Low-Voltage Detect Characteristics ................ 446
High-Voltage Detect Operation (VDIRMAG = 1) ...... 352
I
Example SPI Master Mode (CKE = 1) ..................... 456
Example SPI Master Mode Timing .......................... 455
Example SPI Slave Mode (CKE = 0) ....................... 457
Example SPI Slave Mode (CKE = 1) ....................... 458
External Clock (All Modes except PLL) .................... 449
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 244
Full-Bridge PWM Output .......................................... 195
Half-Bridge PWM Output ................................. 193, 199
High/Low-Voltage Detect Characteristics ................ 446
High-Voltage Detect Operation (VDIRMAG = 1) ...... 352
I
2
I
2
I
2
I
2
I
2
Internal Oscillator Switch Timing ................................ 43
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 351
Master SSP I
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 351
Master SSP I
2
Master SSP I
2
PWM Direction Change ........................................... 196
PWM Direction Change at Near 100% Duty Cycle .. 197
PWM Output (Active-High) ...................................... 191
PWM Output (Active-Low) ....................................... 192
Repeat Start Condition ............................................ 245
Reset, Watchdog Timer (WDT), Oscillator Start-up
PWM Direction Change at Near 100% Duty Cycle .. 197
PWM Output (Active-High) ...................................... 191
PWM Output (Active-Low) ....................................... 192
Repeat Start Condition ............................................ 245
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 287
Slow Rise Time (MCLR Tied to V
Slow Rise Time (MCLR Tied to V
DD
, V
DD
Rise >
T
PWRT
SPI Mode (Master Mode) ......................................... 217
Synchronous Reception (Master Mode, SREN) ...... 292
Synchronous Transmission ..................................... 289
Synchronous Transmission (Through TXEN) .......... 289
Time-out Sequence on POR w/PLL Enabled
Synchronous Reception (Master Mode, SREN) ...... 292
Synchronous Transmission ..................................... 289
Synchronous Transmission (Through TXEN) .......... 289
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD
Time-out Sequence on Power-up (MCLR
Tied to V
DD
, V
DD
Rise < T
PWRT
Timer0 and Timer1 External Clock .......................... 453
Timer1/3/5 Incrementing Edge ................................ 169
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to PRI_RUN
Timer1/3/5 Incrementing Edge ................................ 169
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to PRI_RUN
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
Transition Timing for Wake from Idle to Run Mode ... 53
A/D Conversion Requirements ................................ 464
Capture/Compare/PWM Requirements ................... 455
CLKO and I/O Requirements ................................... 451
EUSART Synchronous Receive Requirements ....... 463
EUSART Synchronous Transmission
Capture/Compare/PWM Requirements ................... 455
CLKO and I/O Requirements ................................... 451
EUSART Synchronous Receive Requirements ....... 463
EUSART Synchronous Transmission
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 456
(Slave Mode, CKE = 0) .................................... 457
(Slave Mode, CKE = 0) .................................... 457
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 450
Reset, Watchdog Timer, Oscillator Start-up Timer,
Reset, Watchdog Timer, Oscillator Start-up Timer,
Top-of-Stack Access .......................................................... 71
TSTFSZ ........................................................................... 413
Two-Speed Clock Start-up Mode ....................................... 42
Two-Speed Start-up ......................................................... 355
Two-Word Instructions
TSTFSZ ........................................................................... 413
Two-Speed Clock Start-up Mode ....................................... 42
Two-Speed Start-up ......................................................... 355
Two-Word Instructions
TxCON (Timer2/4/6) Register .......................................... 177
TxCON Register .............................................................. 172
TxGCON Register ............................................................ 173
TXREG ............................................................................ 269
TXSTA Register ............................................................... 277
TxCON Register .............................................................. 172
TxGCON Register ............................................................ 173
TXREG ............................................................................ 269
TXSTA Register ............................................................... 277