Microchip Technology MA160014 Data Sheet

 2010-2012 Microchip Technology Inc.

DS41412F-page 59

The PIC18(L)F2X/4XK22 devices differentiate between
various kinds of Reset: 

a)

Power-on Reset (POR) 

b)

MCLR Reset during normal operation

c)

MCLR Reset during power-managed modes 

d)

Watchdog Timer (WDT) Reset (during 
execution)

e)

Programmable Brown-out Reset (BOR) 

f)

RESET

 Instruction

g)

Stack Full Reset

h)

Stack Underflow Reset

This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in

WDT Resets are covered in 

.

A simplified block diagram of the On-Chip Reset Circuit
is shown in 

Device Reset events are tracked through the RCON
register (

). The lower five bits of the

register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in

.

The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in

. BOR is covered in

.

External Reset

MCLR

V

DD

OSC1

WDT

Time-out

V

DD

Detect

OST/PWRT

LFINTOSC 

POR

OST

10-bit Ripple Counter

PWRT

11-bit Ripple Counter

Enable OST

Enable PWRT

See 

 for time-out situations.

PWRT and OST counters are reset by POR and BOR. See Sections 

.

Brown-out

Reset

BOREN

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

( )_IDLE

1024 Cycles

65.5 ms

32 

s

MCLRE

S

R

Q

Chip_Reset