Microchip Technology MA160014 Data Sheet
2010-2012 Microchip Technology Inc.
DS41412F-page 67
PIC18(L)F2X/4XK22
4.7
Reset State of Registers
Some registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
is unknown on POR and unchanged by all other
Resets. All other registers are forced to a “Reset state”
depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in
These bits are used by software to determine the
nature of the Reset.
nature of the Reset.
describes the Reset states for all of the
Special Function Registers. The table identifies
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear, WDT Resets, STKFUL, STKUNF, etc.).
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear, WDT Resets, STKFUL, STKUNF, etc.).
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
FOR RCON REGISTER
Condition
Program
Counter
RCON Register
STKPTR Register
SBOREN
RI
TO
PD
POR BOR
STKFUL
STKUNF
Power-on Reset
0000h
1
1
1
1
0
0
0
0
RESET
Instruction
0000h
u
(2)
0
u
u
u
u
u
u
Brown-out Reset
0000h
u
(2)
1
1
1
u
0
u
u
MCLR during Power-Managed
Run Modes
Run Modes
0000h
u
(2)
u
1
u
u
u
u
u
MCLR during Power-Managed
Idle Modes and Sleep Mode
Idle Modes and Sleep Mode
0000h
u
(2)
u
1
0
u
u
u
u
WDT Time-out during Full Power
or Power-Managed Run Mode
or Power-Managed Run Mode
0000h
u
(2)
u
0
u
u
u
u
u
MCLR during Full Power
Execution
Execution
0000h
u
(2)
u
u
u
u
u
u
u
Stack Full Reset (STVREN = 1)
0000h
u
(2)
u
u
u
u
u
1
u
Stack Underflow Reset
(STVREN = 1)
(STVREN = 1)
0000h
u
(2)
u
u
u
u
u
u
1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
actual Reset, STVREN = 0)
0000h
u
(2)
u
u
u
u
u
u
1
WDT Time-out during Power-
Managed Idle or Sleep Modes
Managed Idle or Sleep Modes
PC + 2
u
(2)
u
0
0
u
u
u
u
Interrupt Exit from Power-
Managed Modes
Managed Modes
PC + 2
(1)
u
(2)
u
u
0
u
u
u
u
Legend: u = unchanged
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
interrupt vector (008h or 0018h).
2:
Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
TABLE 4-4:
REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RCON
IPEN
SBOREN
—
RI
TO
PD
POR
BOR
STKPTR
STKFUL
STKUNF
—
STKPTR<4:0>
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.