Microchip Technology DV320032 Data Sheet
PIC32MX330/350/370/430/450/470
DS60001185C-page 138
2012-2013 Microchip Technology Inc.
REGISTER 10-8:
DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ<7:0>
(1)
15:8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CHSIRQ<7:0>
(1)
7:0
S-0
S-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
Legend:
S = Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits
(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
•
•
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8
CHSIRQ<7:0>: Channel Transfer Start IRQ bits
(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 7
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 6
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 5
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
bit 4
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
See
for the list of available interrupt IRQ sources.