Microchip Technology DV320032 Data Sheet
2012-2013 Microchip Technology Inc.
DS60001185C-page 225
PIC32MX330/350/370/430/450/470
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits
(3)
11111111 = Alarm will trigger 256 times
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00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
REGISTER 21-2:
RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
Note 1:
Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
CHIME = 0.
2:
This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3:
This assumes a CPU read will execute in less than 32 PBCLKs.
Note:
This register is reset only on a Power-on Reset (POR).