Microchip Technology DV320032 Data Sheet

DS60001185C-page  286

 2012-2013 Microchip Technology Inc.



(unless otherwise stated)
Operating temperature

-40°C 

 T

A

 

 +85°C for Industrial 

-40°C 

 T

A

 

 +105°C for V-temp 

OS50

F

PLLI

PLL Voltage Controlled 



Oscillator (VCO) Input 



Frequency Range

3.92

—

5

MHz ECPLL, HSPLL, XTPLL, 

FRCPLL modes

OS51

F

SYS

On-Chip VCO System 



Frequency

60

—

120

MHz

—

OS52

T

LOCK

PLL Start-up Time (Lock Time)

—

—

2

ms

—

OS53

D

CLK

CLKO Stability



(Period Jitter or Cumulative)

-0.25

—

+0.25

%

Measured over 100 ms 
period

Note 1: These parameters are characterized, but not tested in manufacturing.

2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for 

individual time-bases on communication clocks, use the following formula:

For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:

----------------------------------------------------------

--------------------------------------------------------------

=

40
20

------

--------------

1.41

--------------

=

=



(unless otherwise stated)
Operating temperature

-40°C 

 T

A

 

 +85°C for Industrial 

-40°C 

 T

A

 

 +105°C for V-temp

F20b

FRC

-0.9

—

+0.9

%

—

Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.



(unless otherwise stated)
Operating temperature

-40°C 

 T

A

 

 +85°C for Industrial 

-40°C 

 T

A

 

 +105°C for V-temp

F21

LPRC

-15

—

+15

%

—

Note 1: Change of LPRC frequency as V

DD

 changes.