Microchip Technology ADM00317 Data Sheet
© 2011-2012 Microchip Technology Inc.
DS22272C-page 9
MCP4706/4716/4726
FIGURE 1-4:
I
2
C Bus Data Timing.
90
91
92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out
TABLE 1-3:
I
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
I
2
C™ AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Temperature
-40
°C ≤ T
A
≤ +125°C (Extended)
Operating Voltage V
DD
range is described in
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock high time
100 kHz mode
4000
—
ns
2.7V-5.5V
400 kHz mode
600
—
ns
2.7V-5.5V
1.7 MHz mode
120
ns
4.5V-5.5V
3.4 MHz mode
60
—
ns
4.5V-5.5V
101
T
LOW
Clock low time
100 kHz mode
4700
—
ns
2.7V-5.5V
400 kHz mode
1300
—
ns
2.7V-5.5V
1.7 MHz mode
320
ns
4.5V-5.5V
3.4 MHz mode
160
—
ns
4.5V-5.5V
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode (400 kHz) I
2
C™ bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but
the requirement t
SU;DAT
≥ 250 ns must then be met. This will automatically be the case if the device does
not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL
signal, it must output the next data bit to the SDA line.
T
signal, it must output the next data bit to the SDA line.
T
R
max.+t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before
the SCL line is released.
3:
The MCP47X6 device must provide a data hold time to bridge the undefined part between V
IH
and V
IL
of
the falling edge of the SCL signal. This specification is not a part of the I
2
C specification, but must be tested
in order to ensure that the output data will meet the setup and hold specifications for the receiving device.
4:
Use C
b
in pF for the calculations.
5:
Not Tested. This parameter ensured by characterization.
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I
not unintentionally create a Start or Stop condition.
If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the
I
2
C bus line. If this parameter is too long, the Data Input Setup (T
SU:DAT
) or Clock Low time (T
LOW
) can be
affected.
Data Input: This parameter must be longer than t
SP
.
Data Output: This parameter is characterized, and tested indirectly by testing T
AA
parameter.
7:
Ensured by the T
AA
3.4 MHz specification test.
8:
The specification is not part of the I
2
C specification. T
AA
= T
HD:DAT
+ T
FSDA
(or T
RSDA
).