Freescale Semiconductor Xtrinsic MAG3110 Magnetometer RD4247MAG3110 RD4247MAG3110 Data Sheet
Product codes
RD4247MAG3110
MAG3110
Sensors
12
Freescale Semiconductor, Inc.
Figure 6. I
2
C timing diagram
4.2.3
Fast Read mode
When the Fast Read (FR) bit is set (CTRL_REG1, 0x10, bit 2), the MSB 8-bit data is read through the I
2
C bus. Auto-increment
is set to skip over the LSB data. When FR bit is cleared, the complete 16-bit data is read accessing all 6 bytes sequentially
(OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB).
(OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB).
4.2.4
User offset corrections
The 2’s complement user offset correction register values are used to compensate for correcting the X, Y, and Z-axis after device
board mount. These values may be used to compensate for hard-iron interference and zero-flux offset of the sensor.
board mount. These values may be used to compensate for hard-iron interference and zero-flux offset of the sensor.
Depending on the setting of the CTRL_REG2[RAW] bit, the magnetic field sample data is corrected with the user offset values
(CTRL_REG2[RAW] = 0), or can be read out uncorrected for user offset values (CTRL_REG2[RAW] = 1).
(CTRL_REG2[RAW] = 0), or can be read out uncorrected for user offset values (CTRL_REG2[RAW] = 1).
The factory calibration for gain, offset and temperature compensation is always automatically applied irrespective of the setting
of the CTRL_REG2[RAW] bit which only controls whether the user offset correction values stored in the OFF_X/Y/Z registers are
applied to the output data. In order to not saturate the sensor output, user written offset values should be within the range of
±10,000 counts.
of the CTRL_REG2[RAW] bit which only controls whether the user offset correction values stored in the OFF_X/Y/Z registers are
applied to the output data. In order to not saturate the sensor output, user written offset values should be within the range of
±10,000 counts.
< Single Byte Read >
Master
ST
Device Address[6:0]
W
Register Address[7:0]
SR
Device Address[6:0]
R
NAK SP
Slave
AK
AK
AK
Data[7:0]
< Multiple Byte Read >
Master
ST
Device Address[6:0]
W
Register Address[7:0]
SR Device Address[6:0]
R
AK
Slave
AK
AK
AK
Data[7:0]
Master
AK
AK
NAK
SP
Slave
Data[7:0]
Data[7:0]
Data[7:0]
< Multiple Byte Write >
Master
ST
Device Address[6:0]
W
Register Address[7:0]
Data[7:0]
Data[7:0]
SP
Slave
AK
AK
AK
AK
< Single Byte Write >
Master
ST
Device Address[6:0]
W
Register Address[7:0]
Data[7:0]
SP
Slave
AK
AK
AK
Legend
ST: Start Condition
SP: Stop Condition
NAK: No Acknowledge
W: Write = 0
SR: Repeated Start Condition
AK: Acknowledge
R: Read = 1