Freescale Semiconductor Xtrinsic MAG3110 Magnetometer RD4247MAG3110 RD4247MAG3110 Data Sheet
Product codes
RD4247MAG3110
MAG3110
Sensors
8
Freescale Semiconductor, Inc.
2.4
I
2
C Interface characteristics
Table 7. I
2
C slave timing values
(1)
1. All values are referred to VIH (min) and VIL (max) levels.
Parameter
Symbol
I
2
C Fast Mode
Unit
Min
Max
SCL clock frequency
Pullup = 1 k
C
b
= 20 pF
f
SCL
0
400
kHz
Bus free time between STOP and START condition
t
BUF
1.3
s
Repeated START hold time
t
HD;STA
0.6
s
Repeated START setup time
t
SU;STA
0.6
s
STOP condition setup time
t
SU;STO
0.6
s
SDA data hold time
(2)
2. t
HD;DAT
is the data hold time that is measured from the falling edge of SCL; the hold time applies to data in transmission and the acknowledge.
t
HD;DAT
0.05
(3)
3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4)
4. The maximum t
HD;DAT
could be must be less than the maximum of t
VD;DAT
or t
VD;ACK
by a transition time. This device may stretch the LOW
period (t
LOW
) of the SCL signal.
s
SDA valid time
(5)
5. t
VD;DAT
= time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
t
VD;DAT
0.9
(4)
s
SDA valid acknowledge time
(6)
6. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
t
VD;ACK
0.9
(4)
s
SDA setup time
t
SU;DAT
100
(7)
7. A Fast mode I
2
C device can be used in a Standard mode I
2
C system, but the requirement t
SU;DAT
250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line t
SCL signal, it must output the next data bit to the SDA line t
r
(max) + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C
specification) before the SCL line is released. Also the acknowledge timing must meet this setup time.
ns
SCL clock low time
t
LOW
1.3
s
SCL clock high time
t
HIGH
0.6
s
SDA and SCL rise time
t
r
20 + 0.1C
b
(8)
1000
ns
SDA and SCL fall time
(3) (8) (9) (10)
8. C
b
= total capacitance of one bus line in pF.
9. The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at 250 ns.
This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified t
the maximum specified t
f
.
10.In Fast mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for
this when considering bus timing.
t
f
20 + 0.1C
b
(8)
300
ns
Pulse width of spikes on SDA and SCL that must be suppressed by input filter
t
SP
50
ns