Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 LAUNCHXL-TMS57004 Data Sheet
Product codes
LAUNCHXL-TMS57004
ASWSTEN
Flash Address Waitstates
EEPROM Emulation Memory Waitstates (Bank 7)
0MHz
0
80MHz
EWAIT
Main Memory Data Waitstates (Bank 0)
RWAIT
0MHz
80MHz
0
1
45MHz
0MHz
2
80MHz
1
3
67MHz
50MHz
SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013
3.3
Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter
Description
Conditions
MIN
MAX
Unit
f
HCLK
HCLK - System clock frequency
80
MHz
f
GCLK
GCLK - CPU clock frequency (ratio f
GCLK
:
f
HCLK
MHz
f
HCLK
= 1:1)
f
VCLK
VCLK - Primary peripheral clock frequency
80
MHz
f
VCLK2
VCLK2 - Secondary peripheral clock
80
MHz
frequency
f
VCLKA1
VCLKA1 - Primary asynchronous
80
MHz
peripheral clock frequency
f
RTICLK
RTICLK - clock frequency
f
VCLK
MHz
3.4
Wait States Required
The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states
required. There are no registers which need to be programmed for RAM wait states.
required. There are no registers which need to be programmed for RAM wait states.
The TCM flash can support zero address and data wait states up to a CPU speed of 45MHz in non-pipelined
mode.The flash supports a maximum CPU clock speed of 80MHz in pipelined mode with no address wait states
and one data wait state.
mode.The flash supports a maximum CPU clock speed of 80MHz in pipelined mode with no address wait states
and one data wait state.
The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN
0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT
0xFFF872B8[19:16]) as shown in
0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT
0xFFF872B8[19:16]) as shown in
below.
Figure 3-1. Wait States Scheme
The flash wrapper defaults to non-pipelined mode with address wait states disabled, ASWSTEN=0; the main
memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.
memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.
Copyright © 2012–2013, Texas Instruments Incorporated
Device Operating Conditions
19
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