Texas Instruments Hercules TMS570LS04x/03x LaunchPad Evaluation Kit LAUNCHXL-TMS57004 LAUNCHXL-TMS57004 Data Sheet
Product codes
LAUNCHXL-TMS57004
/NR
/1 to /64
OSCIN
PLL
INTCLK
/OD
/1 to /8
VCOCLK
/R
/1 to /32
post_ODCLK
/NF
/1 to /256
PLLCLK
f
PLLCLK
= (f
OSCIN
/ NR) * NF / (OD * R)
SPNS186A – OCTOBER 2012 – REVISED SEPTEMBER 2013
4.5.1.3
Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
•
Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.
•
Configurable frequency multipliers and dividers.
•
Built-in PLL Slip monitoring circuit.
•
Option to reset the device on a PLL slip detection.
4.5.1.3.1 Block Diagram
Figure below shows a high-level block diagram of the PLL macro on this microcontroller.
Figure 4-6. PLL Block Diagram
4.5.1.3.2 PLL Timing Specifications
Table 4-11. PLL Timing Specifications
PARAMETER
MIN
MAX
UNIT
f
INTCLK
PLL1 Reference Clock frequency
1
20
MHz
f
post_ODCLK
Post-ODCLK – PLL1 Post-divider input
400
MHz
clock frequency
f
VCOCLK
VCOCLK – PLL1 Output Divider (OD) input
150
550
MHz
clock frequency
4.5.2
Clock Domains
4.5.2.1
Clock Domain Descriptions
The table below lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
system module control register that is used to select an available clock source for each clock domain.
Table 4-12. Clock Domain Descriptions
Clock Domain Name
Default Clock
Clock Source
Description
Source
Selection Register
HCLK
OSCIN
GHVSRC
•
Is disabled via the CDDISx registers bit 1
GCLK
OSCIN
GHVSRC
•
Always the same frequency as HCLK
•
In phase with HCLK
•
Is disabled separately from HCLK via the CDDISx registers bit 0
•
Can be divided by 1 up to 8 when running CPU self-test
(LBIST) using the CLKDIV field of the STCCLKDIV register at
address 0xFFFFE108
(LBIST) using the CLKDIV field of the STCCLKDIV register at
address 0xFFFFE108
GCLK2
OSCIN
GHVSRC
•
Always the same frequency as GCLK
•
2 cycles delayed from GCLK
•
Is disabled along with GCLK
•
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
running CPU self-test (LBIST)
34
System Information and Electrical Specifications
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