Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Data Sheet
Product codes
MPC8309-KIT
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
38
Freescale Semiconductor
eSDHC
The following figure provides the eSDHC clock input timing diagram.
Figure 28. eSDHC clock input timing diagram
The following figure provides the data and command input/output timing diagram.
Figure 29. eSDHC data and command input/output timing diagram referenced to clock
Input hold times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
SD_CLK
t
SHSIXKH
2.5
—
ns
3, 4
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
t
SHSKHOV
–3
3
ns
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first three letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
FHSKHOV
symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the
output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD/SDIO card and 0–20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0–33.25 MHz for an SD/SDIO card and 0–52 MHz for an MMC card.
3. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4. C
4. C
CARD
≤ 10 pF, (1 card), and C
L
= C
BUS
+ C
HOST
+ C
CARD
≤ 40 pF
Table 38. eSDHC AC timing specifications (continued)
At recommended operating conditions with
OV
DD
= 3.3 V
Parameter
Symbol
1
Min
Max
Unit
Notes
eSDHC
t
SHSCKR
External Clock
VM
VM
VM
t
SHSCK
t
SHSCKF
VM = Midpoint Voltage (OV
DD
/2)
operational mode
t
SHSCKL
t
SHSCKH
VM = Midpoint Voltage (OV
DD
/2)
SD_CK
External Clock
SD_DAT/CMD
VM
VM
VM
VM
Inputs
SD_DAT/CMD
Outputs
t
SHSIVKH
t
SHSIXKH
t
SHSKHOV