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Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Data Sheet

Product codes
TWR-S12G240
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Page of 1292
128 KByte Flash Module (S12FTMRG128K1V1)
MC9S12G Family Reference Manual,
Rev.1.23
1044
Freescale Semiconductor
29.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
0x000A
FCCOBHI
R
CCOB15
CCOB14
CCOB13
CCOB12
CCOB11
CCOB10
CCOB9
CCOB8
W
0x000B
FCCOBLO
R
CCOB7
CCOB6
CCOB5
CCOB4
CCOB3
CCOB2
CCOB1
CCOB0
W
0x000C
FRSV1
R
0
0
0
0
0
0
0
0
W
0x000D
FRSV2
R
0
0
0
0
0
0
0
0
W
0x000E
FRSV3
R
0
0
0
0
0
0
0
0
W
0x000F
FRSV4
R
0
0
0
0
0
0
0
0
W
0x0010
FOPT
R
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
W
0x0011
FRSV5
R
0
0
0
0
0
0
0
0
W
0x0012
FRSV6
R
0
0
0
0
0
0
0
0
W
0x0013
FRSV7
R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Address
& Name
7
6
5
4
3
2
1
0
Figure 29-4. FTMRG128K1 Register Summary (continued)