Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Data Sheet
Product codes
TWR-S12G240
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
281
Chapter 6
Interrupt Module (S12SINTV1)
Interrupt Module (S12SINTV1)
6.1
Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
for processing the exception to the CPU. The INT module supports:
•
I bit and X bit maskable interrupt requests
•
A non-maskable unimplemented op-code trap
•
A non-maskable software interrupt (SWI) or background debug mode request
•
Three system reset vector requests
•
A spurious interrupt vector
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
6.1.1
Glossary
contains terms and abbreviations used in the document.
6.1.2
Features
•
Interrupt vector base register (IVBR)
•
One spurious interrupt vector (at address vector base
1
+ 0x0080).
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes
01.02
13 Sep
2007
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
01.03
21 Nov
2007
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
X bit set” feature
01.04
20 May
2009
added footnote about availability of “Wake-up from STOP or WAIT
by XIRQ with X bit set” feature
by XIRQ with X bit set” feature
Table 6-2. Terminology
Term
Meaning
CCR
Condition Code Register (in the CPU)
ISR
Interrupt Service Routine
MCU
Micro-Controller Unit