Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Data Sheet
Product codes
TWR-S12G240
48 KByte Flash Module (S12FTMRG48K1V1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
889
26.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
0x000D
FRSV2
R
0
0
0
0
0
0
0
0
W
0x000E
FRSV3
R
0
0
0
0
0
0
0
0
W
0x000F
FRSV4
R
0
0
0
0
0
0
0
0
W
0x0010
FOPT
R
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
W
0x0011
FRSV5
R
0
0
0
0
0
0
0
0
W
0x0012
FRSV6
R
0
0
0
0
0
0
0
0
W
0x0013
FRSV7
R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R
FDIVLD
FDIVLCK
FDIV[5:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 26-5. Flash Clock Divider Register (FCLKDIV)
Address
& Name
7
6
5
4
3
2
1
0
Figure 26-4. FTMRG48K1 Register Summary (continued)