Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Data Sheet
Product codes
TWR-S12G64-KIT
S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
338
Freescale Semiconductor
8.4.3.3
Immediate Trigger
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
to the TRIG bit in DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into
the Final State, if configured for end alignment, setting the TRIG bit disarms the module, ending the
session and issues a forced breakpoint request to the CPU.
It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of
the current state of ARM.
the current state of ARM.
8.4.3.4
Channel Priorities
In case of simultaneous matches the priority is resolved according to
. The lower priority is
suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher
priority. The priorities described in
priority. The priorities described in
dictate that in the case of simultaneous matches, the match
pointing to final state has highest priority followed by the lower channel number (0,1,2).
8.4.4
State Sequence Control
Figure 8-24. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
Table 8-36. Channel Priorities
Priority
Source
Action
Highest
TRIG
Enter Final State
Channel pointing to Final State
Transition to next state as defined by state control registers
Match0 (force or tag hit)
Transition to next state as defined by state control registers
Match1 (force or tag hit)
Transition to next state as defined by state control registers
Lowest
Match2 (force or tag hit)
Transition to next state as defined by state control registers
State1
Final State
State3
ARM = 1
Session Complete
(Disarm)
State2
State 0
(Disarmed)
ARM = 0
ARM = 0
ARM = 0