Freescale Semiconductor TWR-S12G64 Scalable Platform for Automotive Applications TWR-S12G64-KIT TWR-S12G64-KIT Data Sheet
Product codes
TWR-S12G64-KIT
Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12G Family Reference Manual,
Rev.1.23
588
Freescale Semiconductor
18.2.2
TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
CAN bus:
0 = Dominant state
1 = Recessive state
1 = Recessive state
18.2.3
CAN System
A typical CAN system with MSCAN is shown in
. Each CAN station is connected physically
to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective stations.
needed for the CAN bus and has current protection against defective CAN or defective stations.
Figure 18-2. CAN System
18.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
18.3.1
Module Memory Map
gives an overview on all registers and their individual bits in the MSCAN memory map. The
register address results from the addition of base address and address offset. The base address is
determined at the MCU level and can be found in the MCU memory map description. The address offset
is defined at the module level.
determined at the MCU level and can be found in the MCU memory map description. The address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
CAN Bus
CAN Controller
(MSCAN)
Transceiver
CAN node 1
CAN node 2
CAN node n
CANL
CANH
MCU
TXCAN
RXCAN