Intel 2.80 GHz BX80546KG2800EA Data Sheet
Product codes
BX80546KG2800EA
Intel® Xeon™ Processor with 800 MHz System Bus
18
Datasheet
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide (See
All TESTHI[6:0] pins should be individually connected to V
TT
via a pull-up resistor which
matches the nominal trace impedance. TESTHI[3:0] and TESTHI[6:5] may be tied together and
pulled up to V
pulled up to V
TT
with a single resistor if desired. However, usage of boundary scan test will not be
functional if these pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for
TESTHI[6:0] pins should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values used for
TESTHI[6:0] pins should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50
Ω, then a value between
40
Ω and 60 Ω should be used.
N/C (no connect) pins of the processor are not used by the processor. There is no connection from
the pin to the die. These pins may perform functions in future processors intended for platforms
using the Intel® Xeon™ processor with 800 MHz system bus.
the pin to the die. These pins may perform functions in future processors intended for platforms
using the Intel® Xeon™ processor with 800 MHz system bus.
2.6
Front Side Bus Signal Groups
The front side bus signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF as a reference level. In this document, the term
“AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group
when driving. AGTL+ asynchronous outputs can become active anytime and include an active
pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.
have differential input buffers, which use GTLREF as a reference level. In this document, the term
“AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving.
Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group
when driving. AGTL+ asynchronous outputs can become active anytime and include an active
pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle.
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle.
identifies which signals are common
clock, source synchronous and asynchronous.