Intel 550 LF80537NE0411M User Manual

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Technology is enabled, both logical processors must be halted for performance-monitoring counters 
to be powered down.

• 

The processor is asleep as a result of being halted or because of a power-management scheme. There 

are different levels of sleep. In the some deep sleep levels, the time-stamp counter stops counting.

There are three ways to count processor clock cycles to monitor performance. These are: 

• 

Non-halted clockticks — Measures clock cycles in which the specified logical processor is not 

halted and is not in any power-saving state. When Hyper-Threading Technology is enabled, this 
these ticks can be measured on a per-logical-processor basis.

• 

Non-sleep clockticks — Measures clock cycles in which the specified physical processor is not in a 

sleep mode or in a power-saving state. These ticks cannot be measured on a logical-processor basis.

• 

Time-stamp counter — Some processor models permit clock cycles to be measured when the 

physical processor is not in deep sleep (by using the time-stamp counter and the RDTSC 
instruction). Note that such ticks cannot be measured on a per-logical-processor basis. See Section 
10.8 for detail on processor capabilities.

The first two methods use performance counters and can be set up to cause an interrupt upon overflow 
(for sampling). They may also be useful where it is easier for a tool to read a performance counter than 
to use a time-stamp counter (the timestamp counter is accessed using the RDTSC instruction).  

For applications with a significant amount of I/O, there are two ratios of interest: 

• 

Non-halted CPI  —  Non-halted clockticks/instructions retired measures the CPI for phases where 

the CPU was being used. This ratio can be measured on a logical-processor basis when Hyper-
Threading Technology is enabled.

• 

Nominal CPI — Time-stamp counter ticks/instructions retired measures the CPI over the duration 

of a program, including those periods when the machine halts while waiting for I/O.

 

 

The time-stamp counter increments when the clock signal on the system bus is active and when the sleep 
pin is not asserted. The counter value can be read with the RDTSC instruction. 

The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all 
processors. See Section 10.8 for more information on counter operation. 

 

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