Analog Devices AD7091 Evaluation Board EVAL-AD7091SDZ EVAL-AD7091SDZ Data Sheet
Product codes
EVAL-AD7091SDZ
1 MSPS, Ultralow Power,
12-Bit ADC in 8-Lead LFCSP
Data Sheet
Rev. A
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FEATURES
Fast throughput rate of 1 MSPS
Specified for V
Specified for V
DD
of 2.09 V to 5.25 V
INL of ±1 LSB maximum
Analog input range of 0 V to V
Analog input range of 0 V to V
DD
Ultralow power
367 μA typical at 3 V and 1 MSPS
324 nA typical at 3 V in power-down mode
324 nA typical at 3 V in power-down mode
Reference provided by V
DD
Flexible power/throughput rate management
High speed serial interface: SPI®-/QSPI™-/MICROWIRE®-/
High speed serial interface: SPI®-/QSPI™-/MICROWIRE®-/
DSP-compatible
Busy indicator
Power-down mode
8-lead, 2 mm × 2 mm LFCSP package
Temperature range: −40°C to +125°C
Power-down mode
8-lead, 2 mm × 2 mm LFCSP package
Temperature range: −40°C to +125°C
APPLICATIONS
Battery-powered systems
Handheld meters
Medical instruments
Mobile communications
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Energy harvesting
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Energy harvesting
FUNCTIONAL BLOCK DIAGRAM
CONVERSION
CONTROL LOGIC
GND
CLK
OSC
V
IN
REGCAP
V
DD
12-BIT
SAR
ADC
SERIAL
INTERFACE
SDO
AD7091
SCLK
CS
CONVST
T/H
104
94-
0
01
Figure 1.
0
100
200
300
400
500
600
700
800
900
1000
1100
0
200
400
600
800
1000
PO
W
ER
(
μ
W)
THROUGHPUT RATE (kSPS)
V
DD
= 3V
10
494
-00
2
Figure 2. Power Dissipation vs. Throughput Rate
GENERAL DESCRIPTION
is a 12-bit successive approximation register
analog-to-digital converter (SAR ADC) that offers ultralow
power consumption (typically 367 μA at 3 V and 1 MSPS) while
achieving fast throughput rates (1 MSPS with a 50 MHz SCLK).
The
power consumption (typically 367 μA at 3 V and 1 MSPS) while
achieving fast throughput rates (1 MSPS with a 50 MHz SCLK).
The
operates from a single 2.09 V to 5.25 V power
also features an on-chip conversion clock
and a high speed serial interface.
The conversion process and data acquisition are controlled using
a CONVST signal and an internal oscillator. The
a CONVST signal and an internal oscillator. The
serial interface that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The
while achieving a 1 MSPS throughput rate. The
uses
advanced design and process techniques to achieve very low
power dissipation at high throughput rates.
power dissipation at high throughput rates.
The reference is derived internally from V
DD
. This design allows
the widest dynamic input range to the ADC; that is, the analog
input range for the
input range for the
is from 0 V to V
DD
.
PRODUCT HIGHLIGHTS
1. Lowest Power 12-Bit SAR ADC Available.
2. High Throughput Rate with Ultralow Power Consumption.
3. Flexible Power/Throughput Rate Management.
2. High Throughput Rate with Ultralow Power Consumption.
3. Flexible Power/Throughput Rate Management.
Average power scales with the throughput rate. Power-down
mode allows the average power consumption to be reduced
when the device is not performing a conversion.
mode allows the average power consumption to be reduced
when the device is not performing a conversion.
4. Reference Derived from the Power Supply.
5. Single-Supply Operation.
5. Single-Supply Operation.