Analog Devices ADF4153A Evaluation Board EV-ADF4153ASD1Z EV-ADF4153ASD1Z Data Sheet
Product codes
EV-ADF4153ASD1Z
Fractional-N Frequency Synthesizer
Data Sheet
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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FEATURES
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate V
2.7 V to 3.3 V power supply
Separate V
P
allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with
Consistent RF output phase
Loop filter design possible with ADIsimPLL
Loop filter design possible with ADIsimPLL
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
Wireless LANs, PMR
Communications test equipment
GENERAL DESCRIPTION
The
is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
N-COUNTER
CP
RFCP3 RFCP2 RFCP1
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLK
REF
IN
AV
DD
AGND
V
DD
V
DD
DGND
R
DIV
N
DIV
DGND
CPGND
DV
DD
V
P
SDV
DD
R
SET
RF
IN
A
RF
IN
B
OUTPUT
MUX
–
+
HIGH-Z
PHASE
FREQUENCY
DETECTOR
ADF4153A
THIRD ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
REG
FRACTION
REG
INTEGER
REG
CURRENT
SETTING
×2
DOUBLER
4-BIT
R COUNTER
CHARGE
PUMP
MUXOUT
1
1047-
001
Figure 1.