Analog Devices AD5522 Evaluation Board EVAL-AD5522EBDZ EVAL-AD5522EBDZ Data Sheet
Product codes
EVAL-AD5522EBDZ
AD5522
Data Sheet
Rev. E | Page 58 of 64
APPLICATIONS INFORMATION
POWER-ON DEFAULT
The power-on default for all DAC channels is that the contents
of each M register are set to full scale (0xFFFF), and the contents
of each C register are set to midscale (0x8000). The contents of
the DAC X1 registers at power-on are listed in Table 36.
The power-on default for the alarm status register is 0xFFFFF0,
and the power-on default for the comparator status register is
0x400000. The power-on default values of the PMU register and
the system control register are shown in Table 37 and Table 38.
of each M register are set to full scale (0xFFFF), and the contents
of each C register are set to midscale (0x8000). The contents of
the DAC X1 registers at power-on are listed in Table 36.
The power-on default for the alarm status register is 0xFFFFF0,
and the power-on default for the comparator status register is
0x400000. The power-on default values of the PMU register and
the system control register are shown in Table 37 and Table 38.
SETTING UP THE DEVICE ON POWER-ON
On power-on, default conditions are recalled from the power-
on reset register to ensure that each PMU and DAC channel is
powered up in a known condition. To operate the device, the
user must follow these steps:
1. Configure the device by writing to the system control
on reset register to ensure that each PMU and DAC channel is
powered up in a known condition. To operate the device, the
user must follow these steps:
1. Configure the device by writing to the system control
register to set up different functions as required.
2. Calibrate the device to trim out errors, and load the
required calibration values to the gain (M) and offset (C)
registers. Load codes to each DAC input (X1) register.
When X1 values are loaded to the individual DACs, the
calibration engine calculates the appropriate X2 value and
stores it, ready for the PMU address to call it.
registers. Load codes to each DAC input (X1) register.
When X1 values are loaded to the individual DACs, the
calibration engine calculates the appropriate X2 value and
stores it, ready for the PMU address to call it.
3. Load the required PMU channel with the required force
mode, current range, and so on. Loading the PMU channel
configures the switches around the force amplifier,
measure function, clamps, and comparators, and also acts
as a load signal for the DACs, loading the DAC register
with the appropriate stored X2 value.
configures the switches around the force amplifier,
measure function, clamps, and comparators, and also acts
as a load signal for the DACs, loading the DAC register
with the appropriate stored X2 value.
4. Because the voltage and current ranges have individual
DAC registers associated with them, each PMU register
mode of operation calls a particular X2 register. Therefore,
only updates (that is, changes to the X1 register) to DACs
associated with the selected mode of operation are reflected
in the output of the PMU. If there is a change to the X1
value associated with a different PMU mode of operation,
this X1 value and its M and C coefficients are used to
calculate a corresponding X2 value, which is stored in the
correct X2 register, but this value is not loaded to the DAC.
mode of operation calls a particular X2 register. Therefore,
only updates (that is, changes to the X1 register) to DACs
associated with the selected mode of operation are reflected
in the output of the PMU. If there is a change to the X1
value associated with a different PMU mode of operation,
this X1 value and its M and C coefficients are used to
calculate a corresponding X2 value, which is stored in the
correct X2 register, but this value is not loaded to the DAC.
Table 36. Default Contents of DAC Registers at Power-On
DAC Register
Default Value
Offset DAC
0xA492
FIN DAC
0x8000
CLL DAC
0x0000
CLH DAC
0xFFFF
CPL DAC
0x0000
CPH DAC
0xFFFF
Table 37. Power-On Default for System Control Register
Bit
Bit Name
Default Value
21 (MSB)
CL3
0
20
CL2
0
19
CL1
0
18
CL0
0
17
CPOLH3
0
16
CPOLH2
0
15
CPOLH1
0
14
CPOLH0
0
13
CPBIASEN
0
12
DUTGND/CH
0
11
Guard ALM
0
10
Clamp ALM
0
9
INT10K
0
8
Guard EN
0
7
GAIN1
0
6
GAIN0
0
5
TMP enable
1
4
TMP1
0
3
TMP0
0
2
Latched
0
1
Unused data bit
0
0 (LSB)
Unused data bit
0
Table 38. Power-On Default for PMU Register
Bit
Bit Name
Default Value
21 (MSB)
CH EN
0
20
FORCE1
0
19
FORCE0
0
18
Reserved
0
17
C2
0
16
C1
1
15
C0
1
14
MEAS1
1
13
MEAS0
1
12
FIN
0
11
SF0
0
10
SS0
0
9
CL
0
8
CPOLH
0
7
Compare V/I
0
6
LTMPALM
1
5
TMPALM
1
4
Unused data bit
0
3
Unused data bit
0
2
Unused data bit
0
1
Unused data bit
0
0 (LSB)
Unused data bit
0