Analog Devices AD9211 Evaluation Board AD9211-200EBZ AD9211-200EBZ Data Sheet
Product codes
AD9211-200EBZ
10-Bit, 200 MSPS/250 MSPS/300 MSPS,
1.8 V Analog-to-Digital Converter
AD9211
Rev. 0
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FEATURES
SNR = 60.1 dBFS @ f
IN
up to 70 MHz @ 300 MSPS
ENOB of 9.7 @ f
IN
up to 70 MHz @ 300 MSPS (−1.0 dBFS)
SFDR = −80 dBc @ f
IN
up to 70 MHz @ 300 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.2 LSB typical
INL = ±0.2 LSB typical
LVDS at 300 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
437 mW @ 300 MSPS—LVDS SDR mode
410 mW @ 300 MSPS—LVDS DDR mode
410 mW @ 300 MSPS—LVDS DDR mode
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD (1.8V)
VIN+
VIN–
TRACK-AND-HOLD
REFERENCE
ADC
10-BIT
CORE
OUTPUT
STAGING
LVDS
CLK+
CLK–
CLOCK
MANAGEMENT
SERIAL PORT
RESET SCLK SDIO CSB
DCO–
DCO+
OR–
OR+
D9 TO D0
DGND
DRVDD
10
10
AD9211
PWDN
RBIAS
0
6041-
001
Figure 1.
GENERAL DESCRIPTION
The AD9211 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 300 MSPS conversion
rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete
signal conversion solution.
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 300 MSPS conversion
rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete
signal conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9211 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 60.1 dBFS SNR @
300 MSPS with a 70 MHz input.
2. Low Power—Consumes only 410 mW @ 300 MSPS.
3. Ease of Use—LVDS output data and output clock signal
3. Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface
supports various product functions, such as data
formatting, disabling the clock duty cycle stabilizer, power-
down, gain adjust, and output test pattern generation.
formatting, disabling the clock duty cycle stabilizer, power-
down, gain adjust, and output test pattern generation.
5. Pin-Compatible Family—12-bit pin-compatible family
offered as AD9230.