Analog Devices AD9129 Evaluation Board AD9129-MIX-EBZ AD9129-MIX-EBZ Data Sheet
Product codes
AD9129-MIX-EBZ
11-/14-Bit, 5.7 GSPS,
RF Digital-to-Analog Converter
Data Sheet
Rev. A
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FEATURES
DAC update rate: up to 5.7 GSPS
Direct RF synthesis at 2.85 GSPS data rate
Direct RF synthesis at 2.85 GSPS data rate
DC to 1.425 GHz in baseband mode
DC to 1.0 GHz in 2× interpolation mode
1.425 GHz to 4.2 GHz in Mix-Mode
DC to 1.0 GHz in 2× interpolation mode
1.425 GHz to 4.2 GHz in Mix-Mode
Bypassable 2× interpolation
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
Excellent dynamic performance
Supports DOCSIS 3.0 wideband ACLR/harmonic performance
8 QAM carriers: ACLR > 65 dBc
Industry-leading single/multicarrier IF or RF synthesis
4-carrier W-CDMA ACLR at 2457.6 MSPS
f
OUT
= 900 MHz, ACLR = 71 dBc (baseband mode)
f
OUT
= 2100 MHz, ACLR = 68 dBc (Mix-Mode)
f
OUT
= 2700 MHz, ACLR = 67 dBc (Mix-Mode)
Dual-port LVDS and DHSTL data interface
Up to 1.425 GSPS operation
Source synchronous DDR clocking with parity bit
Source synchronous DDR clocking with parity bit
Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS)
APPLICATIONS
Broadband communications systems
CMTS/VOD
Wireless infrastructure: W-CDMA, LTE, point-to-point
Wireless infrastructure: W-CDMA, LTE, point-to-point
Instrumentation, automatic test equipment (ATE)
Radar, jammers
Radar, jammers
FUNCTIONAL BLOCK DIAGRAM
SDO
SDIO
SCLK
CS
DCI_x
DAT
A AS
S
E
M
BL
E
R
SPI
RESET
Tx DAC
CORE
DAT
A
L
AT
CH
IOUTP
IOUTN
IRQ
4
×
FI
FO
2×
BASEBAND
MODE
MIX-
MODE
FRM_x
(FRAME/
PARITY)
AD9129
CLOCK
DISTRIBUTION
VREF
I250U
L
V
DS
DDR
R
EC
EI
VER
L
V
DS
DDR
R
EC
EI
VER
P1_D[13:0]P,
P1_D[13:0]N
P0_D[13:0]P,
P0_D[13:0]N
DLL
1.2V
PLL
DCO_x
NORMAL
11
149-
001
DACCLK_x
DCR
Figure 1.
GENERAL DESCRIPTION
The
are high performance, 11-/14-bit RF digital-
to-analog converters (DACs) supporting data rates up to 2.85
GSPS. The DAC core is based on a quad-switch architecture that
enables dual-edge clocking operation, effectively increasing the
DAC update rate to 5.7 GSPS when configured for Mix-Mode™
or 2× interpolation. The high dynamic range and bandwidth
GSPS. The DAC core is based on a quad-switch architecture that
enables dual-edge clocking operation, effectively increasing the
DAC update rate to 5.7 GSPS when configured for Mix-Mode™
or 2× interpolation. The high dynamic range and bandwidth
enable multicarrier generation up to 4.2 GHz.
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the
In baseband mode, wide bandwidth capability combines with high
dynamic range to support from 1 to 158 contiguous carriers for
CATV infrastructure applications. A choice of two optional 2×
interpolation filters is available to simplify the postreconstruction
filter by effectively increasing the DAC update rate by a factor of 2.
In Mix-Mode operation, the
RF carriers in the second and third Nyquist zone while still
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
maintaining exceptional dynamic range up to 4.2 GHz. The
high performance NMOS DAC core features a quad-switch
architecture that enables industry-leading direct RF synthesis
performance with minimal loss in output power. The output
current can be programmed over a range of 9.5 mA to 34.4 mA.
simplify system integration. A dual-port, source synchronous
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
LVDS interface simplifies the data interface to a host FPGA/ASIC.
A differential frame/parity bit is also included to monitor the
integrity of the interface. On-chip delay locked loops (DLLs)
are used to optimize timing between different clock domains.
A serial peripheral interface (SPI) is used to configure the
A serial peripheral interface (SPI) is used to configure the
and monitor the status of readback registers.
is manufactured on a 0.18 µm CMOS
process and operates from +1.8 V and −1.5 V supplies. It is
supplied in a 160-ball chip scale package ball grid array.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
support RF signal synthesis of up to 4.2 GHz.
2. Dual-port interface with double data rate (DDR) LVDS
data receivers supports 2850 MSPS maximum conversion rate.
3. Manufactured on a CMOS process; a proprietary switching
technique enhances dynamic performance.